// module name: ALU_CTL 
// author: yangtao2019
// date: 2021.07.10

`timescale 1ns / 1ps

module ALU_CTL(
    input[1:0] ALUOp,
    input[3:0] funct7and3,
    output[3:0] alu_ctl
);
    // funct7and3[3]: funct7 I[30]
    // funct7and3[2]: funct3 I[14]
    // funct7and3[1]: funct3 I[13]
    // funct7and3[0]: funct3 I[12]

    assign alu_ctl =    (ALUOp==2'b00)? 4'b0010 :                   //add
                        (ALUOp==2'b01)? 4'b0110 :                   //subtract
                        (ALUOp==2'b11)? 4'b1111 :                   //Shift left
                        // indicates ALUOp==2'b1x
                        (funct7and3[3]==1'b1)? 4'b0110:             //substract
                        // funct7and3[3] = 0
                        (funct7and3[2:0]==3'b000)? 4'b0010:         //add
                        (funct7and3[2:0]==3'b111)? 4'b0000:         //AND
                        (funct7and3[2:0]==3'b000)? 4'b0001:         //OR
                        // a illgeal code, wihch could trigger error
                        4'b1111;                                    //default


endmodule